Definition

enum {
    /* Joypad and Serial */
    GB_IO_JOYP       = 0x00, // Joypad (R/W)
    GB_IO_SB         = 0x01, // Serial transfer data (R/W)
    GB_IO_SC         = 0x02, // Serial Transfer Control (R/W)

    /* Missing */

    /* Timers */
    GB_IO_DIV        = 0x04, // Divider Register (R/W)
    GB_IO_TIMA       = 0x05, // Timer counter (R/W)
    GB_IO_TMA        = 0x06, // Timer Modulo (R/W)
    GB_IO_TAC        = 0x07, // Timer Control (R/W)

    /* Missing */

    GB_IO_IF         = 0x0F, // Interrupt Flag (R/W)

    /* Sound */
    GB_IO_NR10       = 0x10, // Channel 1 Sweep register (R/W)
    GB_IO_NR11       = 0x11, // Channel 1 Sound length/Wave pattern duty (R/W)
    GB_IO_NR12       = 0x12, // Channel 1 Volume Envelope (R/W)
    GB_IO_NR13       = 0x13, // Channel 1 Frequency lo (Write Only)
    GB_IO_NR14       = 0x14, // Channel 1 Frequency hi (R/W)
    /* NR20 does not exist */
    GB_IO_NR21       = 0x16, // Channel 2 Sound Length/Wave Pattern Duty (R/W)
    GB_IO_NR22       = 0x17, // Channel 2 Volume Envelope (R/W)
    GB_IO_NR23       = 0x18, // Channel 2 Frequency lo data (W)
    GB_IO_NR24       = 0x19, // Channel 2 Frequency hi data (R/W)
    GB_IO_NR30       = 0x1A, // Channel 3 Sound on/off (R/W)
    GB_IO_NR31       = 0x1B, // Channel 3 Sound Length
    GB_IO_NR32       = 0x1C, // Channel 3 Select output level (R/W)
    GB_IO_NR33       = 0x1D, // Channel 3 Frequency's lower data (W)
    GB_IO_NR34       = 0x1E, // Channel 3 Frequency's higher data (R/W)
    /* NR40 does not exist */
    GB_IO_NR41       = 0x20, // Channel 4 Sound Length (R/W)
    GB_IO_NR42       = 0x21, // Channel 4 Volume Envelope (R/W)
    GB_IO_NR43       = 0x22, // Channel 4 Polynomial Counter (R/W)
    GB_IO_NR44       = 0x23, // Channel 4 Counter/consecutive, Initial (R/W)
    GB_IO_NR50       = 0x24, // Channel control / ON-OFF / Volume (R/W)
    GB_IO_NR51       = 0x25, // Selection of Sound output terminal (R/W)
    GB_IO_NR52       = 0x26, // Sound on/off

    /* Missing */

    GB_IO_WAV_START  = 0x30, // Wave pattern start
    GB_IO_WAV_END    = 0x3F, // Wave pattern end

    /* Graphics */
    GB_IO_LCDC       = 0x40, // LCD Control (R/W)
    GB_IO_STAT       = 0x41, // LCDC Status (R/W)
    GB_IO_SCY        = 0x42, // Scroll Y (R/W)
    GB_IO_SCX        = 0x43, // Scroll X (R/W)
    GB_IO_LY         = 0x44, // LCDC Y-Coordinate (R)
    GB_IO_LYC        = 0x45, // LY Compare (R/W)
    GB_IO_DMA        = 0x46, // DMA Transfer and Start Address (W)
    GB_IO_BGP        = 0x47, // BG Palette Data (R/W) - Non CGB Mode Only
    GB_IO_OBP0       = 0x48, // Object Palette 0 Data (R/W) - Non CGB Mode Only
    GB_IO_OBP1       = 0x49, // Object Palette 1 Data (R/W) - Non CGB Mode Only
    GB_IO_WY         = 0x4A, // Window Y Position (R/W)
    GB_IO_WX         = 0x4B, // Window X Position minus 7 (R/W)

    // Controls DMG mode and PGB mode
    GB_IO_KEY0       = 0x4C,

    /* General CGB features */
    GB_IO_KEY1       = 0x4D, // CGB Mode Only - Prepare Speed Switch

    /* Missing */

    GB_IO_VBK        = 0x4F, // CGB Mode Only - VRAM Bank
    GB_IO_BANK       = 0x50, // Write to disable the boot ROM mapping

    /* CGB DMA */
    GB_IO_HDMA1      = 0x51, // CGB Mode Only - New DMA Source, High
    GB_IO_HDMA2      = 0x52, // CGB Mode Only - New DMA Source, Low
    GB_IO_HDMA3      = 0x53, // CGB Mode Only - New DMA Destination, High
    GB_IO_HDMA4      = 0x54, // CGB Mode Only - New DMA Destination, Low
    GB_IO_HDMA5      = 0x55, // CGB Mode Only - New DMA Length/Mode/Start

    /* IR */
    GB_IO_RP         = 0x56, // CGB Mode Only - Infrared Communications Port

    /* Missing */

    /* CGB Palettes */
    GB_IO_BGPI       = 0x68, // CGB Mode Only - Background Palette Index
    GB_IO_BGPD       = 0x69, // CGB Mode Only - Background Palette Data
    GB_IO_OBPI       = 0x6A, // CGB Mode Only - Object Palette Index
    GB_IO_OBPD       = 0x6B, // CGB Mode Only - Object Palette Data
    GB_IO_OPRI       = 0x6C, // Affects object priority (X based or index based)

    /* Missing */

    GB_IO_SVBK       = 0x70, // CGB Mode Only - WRAM Bank
    GB_IO_PSM        = 0x71, // Palette Selection Mode, controls the PSW and key combo
    GB_IO_PSWX       = 0x72, // X position of the palette switching window
    GB_IO_PSWY       = 0x73, // Y position of the palette switching window
    GB_IO_PSW        = 0x74, // Key combo to trigger the palette switching window
    GB_IO_UNKNOWN5   = 0x75, // (8Fh) - Bit 4-6 (Read/Write)
    GB_IO_PCM12      = 0x76, // Channels 1 and 2 amplitudes
    GB_IO_PCM34      = 0x77, // Channels 3 and 4 amplitudes
};

enum {
    GB_LCDC_BG_EN = 1,
    GB_LCDC_OBJ_EN = 2,
    GB_LCDC_OBJ_SIZE = 4,
    GB_LCDC_BG_MAP = 8,
    GB_LCDC_TILE_SEL = 0x10,
    GB_LCDC_WIN_ENABLE = 0x20,
    GB_LCDC_WIN_MAP = 0x40,
    GB_LCDC_ENABLE = 0x80,
};

In gb.h

Description

Constants for accessing memory-mapped IO registers. GB_IO_* constants are offsets from the MMIO base (0xFF00). GB_LCDC_* constants are bit masks for the LCDC register.

See Also

• GB_read_memory
• GB_write_memory
• GB_get_direct_access